岗位大厅/Engineering/DFT Engineer CH, UK

Kandou AI · 87天前 · 来源 ATS 官方

DFT Engineer CH, UK

Saint-Sulpice办公方式未标注
全职Engineering
薪资未披露

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🛡 申请链接 2026-10-26 核验有效

📈 该公司近 30 天发布 42 个岗位——扩张招聘中,属加分信号

信号由后台自动核验生成,仅供参考;判断权在你。设计案:GHOST-JOB-P1

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必备技能

AutomationVerilog

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职位描述

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK

Key Responsibilities:

- Hierarchical MBIST and scan insertion, BSD implementation

- ATPG pattern generation, coverage analysis, converging to high coverage metrics

- Pattern simulations with timing

- Defining test mode timing constraints, analyzing the timing reports and converge timing

- Developing cycle accurate functional patterns using IJTAG methodology

- Closely working with the test and production engineering teams to debug and bring up devices at probe and final test

- Debugging silicon issues

Skills:

- Excellent communication skills, and strong team player with can do type of attitude

- Excellent debugging skills

- Good scripting skills to develop automation

Qualifications:

- 5+ years of DFT experience including implementation, test pattern development, and simulation

- Proven experience in contributing to DFT solution to complex designs

- Experience working with IJTAG methodologies

- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies

- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics

- Good debug capabilities in simulating patterns with timing

- Experience with industry standard EDA tools for DFT, timing, and simulation

- Knowledge of System Verilog

Education:

- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

🈯 翻译这份 JD · 红灯 0 / 黄灯 0 / 绿灯 0点开 ▾
没扫到常见信号词。这份 JD 直白得不常见——面试里照常确认节奏、汇报线和薪酬范围就好。
没扫到常见信号词——这份 JD 直白得不常见。照常确认节奏、汇报线和薪酬范围。
词典只标"常见信号",不对公司下结论——红灯 = 面试里该当面确认的问题。想自己翻别的 JD:JD 翻译器 →
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公司 · Company

Kandou AI

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Saint-Sulpice来源:ATS 官方

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