岗位大厅/Other/DFT - Full Time

Kandou AI · 64天前 · 来源 ATS 官方

DFT - Full Time

Hyderabad办公方式未标注
全职Other
薪资未披露

🛡 岗位真实性核验

Ghost Job 检测

⏳ 岗位入库已 2 天

🛡 申请链接 2026-10-26 核验有效

📈 该公司近 30 天发布 42 个岗位——扩张招聘中,属加分信号

信号由后台自动核验生成,仅供参考;判断权在你。设计案:GHOST-JOB-P1

🎯

必备技能

AutomationPCIeSerDesVerilog

免费注册后解锁"你的匹配分 vs 高分画像"与个人技能缺口。

💼

职位描述

Key Responsibilities:

- Lead DFT activity for the next generation products

- Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs

- Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout

- Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development

- Define the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program

- Closely working with the cross functional teams to bring up device qualification solution for HTOL

- Drive lab bench silicon debug to understand ATE bring up issues

Skills:

- Excellent communication skills, and strong team player with can do type of attitude

- Mentoring the team members

- Excellent debugging skills

- Process oriented to drive automation to help increase productivity and quality

Qualifications:

- 12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation

- Proven track record of delivering DFT solution to complex designs

- Experience working with IJTAG methodologies, understanding device functionality

- Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies

- Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics

- Strong debug capabilities in simulating patterns with timing

- Experience in defining test mode constraints and analyzing the timing reports

- Experience with industry standard EDA tools for DFT, timing, and simulation

- Good knowledge of System Verilog

- Experience with chiplet based designs is a plus

Education:

- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or higher)

🈯 翻译这份 JD · 红灯 0 / 黄灯 0 / 绿灯 1点开 ▾
可以投——没有红灯,黄灯问题放进面试清单问清即可。
plus → 加分项,不是门槛
词典只标"常见信号",不对公司下结论——红灯 = 面试里该当面确认的问题。想自己翻别的 JD:JD 翻译器 →
🏢

公司 · Company

Kandou AI

—

Hyderabad来源:ATS 官方

⚑ 岗位信息收录自公开招聘页(ATS 官方),以雇主官网为准